1 pin functions pin name function a0, a1, a2 address inputs sda serial data/address scl serial clock wp write protect v cc +1.8v to +5.5v power supply v ss ground nc no connect description the cat24fc64 is a 64k-bit serial cmos eeprom internally organized as 8,192 words of 8 bits each. catalysts advanced cmos technology substantially reduces device power requirements. the cat24fc64 preliminary information * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. features a 64-byte page write buffer. the device oper- ates via the i 2 c bus serial interface and is available in 8- pin dip or 8-pin soic packages. pin configuration block diagram cat24fc64 64k-bit i 2 c serial cmos eeprom fast mode i 2 c bus compatible* max clock frequency: - 400khz for vcc=1.8v to 5.5v - 1mhz for vcc=2.5v to 5.5v schmitt trigger filtered inputs for noise suppression low power cmos technology 64-byte page write buffer self-timed write cycle with auto-clear features dip package (p, l) soic package (j, w, k, x) ? 2004 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1046, rev. d industrial and automotive temperature ranges 5 ms max write cycle time write protect feature C entire array protected when wp at v ih 1,000,000 program/erase cycles 100 year data retention 8-pin dip, 8-pin soic (jedec), 8-pin soic (eiaj), 8-pin tssop and tdfn packages a1 a2 v ss a1 a2 v cc wp scl sda 1 2 3 4 8 7 6 5 a0 v cc wp scl sda 1 2 3 4 8 7 6 5 v ss a0 tdfn package (rd2, zd2) 1 2 3 4 8 7 6 5 a0 a1 a2 vss v cc wp scl sda (top view) d out ack sense amps shift registers control logic word address buffers start/stop logic state counters slave address comparators eeprom 128x512 v cc external load column decoders xdec data in storage high voltage/ timing control v ss wp scl sda 128 512 a0 a1 a2 h a l o g e n f r e e tm l e a d f r e e a1 a2 a0 v cc wp scl sda 1 2 3 4 8 7 6 5 v ss tssop package (u, y)
preliminary information cat24fc64 2 doc. no. 1046, rev. d absolute maximum ratings* temperature under bias ................. C 55 c to +125 c storage temperature ....................... C 65 c to +150 c voltage on any pin with respect to ground (1) ........... C 2.0v to +v cc + 2.0v v cc with respect to ground ............... C 2.0v to +7.0v *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. note: (1) the minimum dc input voltage is C 0.5v. during transitions, inputs may undershoot to C 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1v to v cc +1v. (5) standby current (i sb ) = 0 a (<900 na). symbol parameter test conditions min typ max units i cc1 power supply current - read f scl = 100 khz 1 ma v cc =5v i cc2 power supply current - write f scl = 400khz 3 ma v cc =5v i sb (5) standby current v in = gnd or v cc 0 a v cc =5v i li input leakage current v in = gnd to v cc 1 a i lo output leakage current v out = gnd to v cc 1 a v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage (v cc = +3.0v) i ol = 3.0 ma 0.4 v v ol2 output low voltage (v cc = +1.8v) i ol = 1.5 ma 0.5 v reliability characteristics symbol parameter reference test method min typ max units n end (3) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (3) data retention mil-std-883, test method 1008 100 years v zap (3) esd susceptibility mil-std-883, test method 3015 4000 volts i lth (3)(4) latch-up jedec standard 17 100 ma capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test conditions min typ max units c i/o (3) input/output capacitance (sda) v i/o = 0v 8 pf c in (3) input capacitance (scl, wp, a0, a1) v in = 0v 6 pf z wpl wp input impedance v in 0.5v 5 70 k ? z wph wp input impedance v in >0.7vxv cc 500 k ? d.c. operating characteristics v cc = +1.8v to +5.5v, unless otherwise specified. package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma
preliminary information cat24fc64 3 doc. no. 1046, rev. d note: (1) ac measurement conditions: rl (connects to v cc ): 0.3v cc to 0.7 v cc input rise and fall times: < 50ns input and output timing reference voltages: 0.5 v cc (2) this parameter is tested initially and after a design or process change that affects the parameter. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. a.c. characteristics v cc = +1.8v to +5.5v, unless otherwise specified output load is 1 ttl gate and 100pf read & write cycle limits power-up timing (2)(3) symbol parameter min typ max units t pur power-up to read operation 100 s t puw power-up to write operation 100 s l o b m y sr e t e m a r a pv 5 . 5 - v 8 . 1 = c c vv 5 . 5 - v 5 . 2 = c c v n i mx a mn i mx a ms t i n u f l c s y c n e u q e r f k c o l c0 0 40 0 0 1z h k t a a d n a t u o a t a d a d s o t w o l l c s t u o k c a 5 0 . 09 . 05 0 . 05 . 0s t f u b ) 2 ( e r o f e b e e r f e b t s u m s u b e h t e m i t t r a t s n a c n o i s s i m s n a r t w e n a 3 . 15 . 0s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s6 . 05 2 . 0s t w o l d o i r e p w o l k c o l c3 . 16 . 0s t h g i h d o i r e p h g i h k c o l c6 . 04 . 0s t a t s : u s a r o f ( e m i t p u t e s n o i t i d n o c t r a t s ) n o i t i d n o c t r a t s d e t a e p e r 6 . 05 2 . 0s t t a d : d h e m i t d l o h n i a t a d00s n t t a d : u s e m i t p u t e s n i a t a d0 0 10 0 1s n t r ) 2 ( e m i t e s i r l c s d n a a d s0 23 . 01 . 0s t f ) 2 ( e m i t l l a f l c s d n a a d s0 20 0 30 0 1s n t o t s : u s e m i t p u t e s n o i t i d n o c p o t s6 . 05 2 . 0s t h d e m i t d l o h t u o a t a d0 50 5s n t r w e m i t e l c y c e t i r w55s m t p s ) l c s , a d s ( n o i s s s e r p p u s t u p n i0 50 5s n t p w ; u s e m i t p u t e s p w6 . 05 . 0s t p w ; d h e m i t d l o h p w3 . 18 . 0s
preliminary information cat24fc64 4 doc. no. 1046, rev. d functional description the cat24fc64 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat24fc64 operates as a slave device. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. pin descriptions scl: serial clock the serial clock input clocks all data transferred into or out of the device. sda: serial data/address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. wp: write protect this input, when tied to gnd, allows write operations to the entire memory. when this pin is tied to vcc, the entire memory is write protected. when left floating, memory is unprotected. 5020 fhd f05 figure 3. start/stop timing figure 2. write cycle timing figure 1. bus timing start bit sda stop bit scl 5020 fhd f04 t wr stop condition start condition address ack 8th bit byte n scl sda 5020 fhd f03 t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh a0, a1, a2: device address inputs these pins are hardwired or left connected. when hardwired, up to eight cat24fc64's may be addressed on a single bus system. when the pins are left unconnected, the default values are zero.
preliminary information cat24fc64 5 doc. no. 1046, rev. d the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat24fc64 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 1010 (fig. 5). the cat24fc64 uses the next three bits as address bits. the address bits a2, a1 and a0 allow figure 4. acknowledge timing figure 5. slave address bits acknowledge 1 start scl from master 89 data output from transmitter data output from receiver as many as eight devices on the same bus. these bits must compare to their hardwired input pins. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat24fc64 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat24fc64 then performs a read or write operation depending on the state of the r/w bit. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat24fc64 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. when the cat24fc64 begins a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat24fc64 will continue to transmit i 2 c bus protocol 1 0 1 0 a2 a1 a0 r/w
preliminary information cat24fc64 6 doc. no. 1046, rev. d data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends two 8-bit address words that are to be written into the address pointers of the cat24fc64. after receiving another acknowledge from the slave, the master device transmits the data to be written into the addressed memory location. the cat24fc64 acknowledges once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to nonvolatile memory. while the cycle is in progress, the device will not respond to any request from the master device. page write the cat24fc64 writes up to 64 bytes of data, in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to 63 additional bytes. after each byte has been transmitted, cat24fc64 will respond with an acknowledge, and internally increment the six low order address bits by one. the high order bits remain un- changed. if the master transmits more than 64 bytes before sending the stop condition, the address counter wraps around , and previously transmitted data will be overwritten. when all 64 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the cat24fc64 in a single write cycle. acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, cat24fc64 initiates the internal write cycle. ack poll- ing can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if cat24fc64 is still busy with the write operation, no ack will be returned. if cat24fc64 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection the write protection feature allows the user to protect against inadvertent programming of the memory array. if the wp pin is tied to v cc , the entire memory array is protected and becomes read only. the cat24fc64 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device s failure to send an acknowledge after the first byte of data is received. figure 7. page write timing figure 6. byte write timing * =don't care bit * =don't care bit a 15 C a 8 slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t a 7 C a 0 byte address a c k * ** a 15 C a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 C a 0 byte address data n+63 data a c k s t o p a c k data n a c k p a c k * * *
preliminary information cat24fc64 7 doc. no. 1046, rev. d read operations the read operation for the cat24fc64 is initiated in the same manner as the write operation with one exception, that r/ w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. immediate/current address read the cat24fc64 s address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n+1. if n=e (where e=8,191), then the counter will wrap around to address 0 and continue to clock out data. after the cat24fc64 receives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. the master device does not send an acknowledge, but will generate a stop condition. selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte addresses of the location it wishes to read. after cat24fc64 acknowledges, the master device sends the start condition and the slave address again, this time with the r/ w bit set to one. the cat24fc64 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat24fc64 sends the initial 8-bit byte requested, the master will respond with an acknowledge which tells the device it requires more data. the cat24fc64 will continue to output an 8-bit byte for each acknowledge sent by the master. the operation will terminate when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from cat24fc64 is outputted sequentially with data from address n followed by data from address n+1. the read operation address counter increments all of the cat24fc64 address bits so that the entire memory array can be read during one operation. if more than e (where e=8,191) bytes are read out, the counter will wrap around and continue to clock out data bytes. figure 8. immediate address read timing scl sda 8th bit stop no ack data out 89 slave address s a c k bus activity: master sda line s t a r t n o a c k data s t o p p
preliminary information cat24fc64 8 doc. no. 1046, rev. d figure 9. selective read timing figure 10. sequential read timing bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address * =don't care bit a 15 C a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 C a 0 byte address slave address s a c k n o a c k s t a r t data p s t o p * **
preliminary information cat24fc64 9 doc. no. 1046, rev. d ordering information notes: (1) the device used in the above example is a 24fc64ji-1.8te13 (soic, industrial temperature, 1.8 volt to 5.5 volt operating voltage, tape & reel) temperature range i = industrial (-40 ? to 85 ? c) a = automotive (-40 ? to 105 ? c) prefix device # suffix j i te13 product number tape & reel te13: 2000/reel package p: pdip k: soic (eiaj) j: soic (jedec) u: tssop rd2: tdfn (4.9x3mm) l: pdip (lead free, halogen free) w: soic, jedec (lead free, halogen free) y: tssop (lead free, halogen free) x: soic, eiaj (lead free, halogen free) zd2: tdfn (4.9x3mm) (lead free, halogen free) operating voltage blank: 2.5 to 5.5v 1.8: 1.8 to 5.5v -1.8 24fc64 cat optional company id e = extended (-40 ? c to 125 ? c)
preliminary information cat24fc64 10 doc. no. 1046, rev. d catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1046 revison: d issue date: 3/26/04 type: preliminary copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date rev. reason 3/3/2004 c added 8-pin tssop package (updated in all areas) updated dc operating characteristics updated power-up timing 3/26/2004 d changed advance designation to preliminary
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